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>Memory testing with cache >Permalink Submitted by krishnakoyalmannam on Thu, 2011-05-19 02:00. When you are testing external DDR2 memory on a multicore system, with a shared Level 2 Cache, each core could be assigned a dedicated section of memory to test and all the cores memory tests in parallel. This causes the L2 cache to result in more cache miss than cache hit, thereby resulting in increased DRAM bus transactions, which could be very useful during HW Board BringUp. And yes, the ground bounce and cross-talk tests do check for signal integrity problems. There is also MARCH-B and MARCH-C memory testing algorithms that sweep memory with random patterns in one direction and sweep in the reverse direction, so, a cache flush would be required before starting the reverse sweep. And finally, an XOR test to uncover memory cell faults, would make the suite of memory tests quite comprehensive providing greater coverage.